Low Power Level-Up Shifter for Reduction of Static Power Dissipation in CMOS Technology

Static power dissipation is increases with the scaling in threshold voltage and expected to become important part of total power consumption. In the present work, a new configuration of level shifters for low power application in 0.25μm technology has been presented. The proposed circuits utilize the merit of stacking technique by which there is reduction in leakage power. In this work a new level-up shifter designed at ultra low core voltage and has wide range of I/O voltage. The circuit is designed using 0.25μm CMOS process. Proposed level shifter uses stacking technique to reduce static power dissipation with a little addition in area. Less static power dissipation allow level shifter suitability for wide I/O interface voltage applications in CMOS Technology with very little power dissipation. Keywords—CMOS, Static Power Dissipation, Level Shifter Threshold voltage, Ultra Low Core Voltage and Stacking Technique.